Browse Prior Art Database

2 Bit Cell Eeprom Cell using Band to Band Tunneling for Data Read Out

IP.com Disclosure Number: IPCOM000110189D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 5 page(s) / 178K

Publishing Venue

IBM

Related People

Acovic, A: AUTHOR

Abstract

Disclosed is a new non-volatile memory cell that stores 2 bits of data in each MOSFET. The cell uses channel hot-electron injection for writing, band to band tunnel injection of holes or electron detrapping for erasing, and band to band tunneling for data readout. The cell is especially well-suited for dense memories, which require a small number of read and write cycles.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

2 Bit Cell Eeprom Cell using Band to Band Tunneling for Data Read Out

       Disclosed is a new non-volatile memory cell that stores 2
bits of data in each MOSFET.  The cell uses channel hot-electron
injection for writing, band to band tunnel injection of holes or
electron detrapping for erasing, and band to band tunneling for data
readout.  The cell is especially well-suited for dense memories,
which require a small number of read and write cycles.

      In usual electrically alterable memory cells (EEPROMs), the
state of the memory cell is read by detecting changes in the channel
current of a MOSFET, due to charges that are trapped either in a
floating gate or in traps inside the gate insulator.  Instead of the
channel current, in the disclosed cell changes in the reverse bias
tunnel current of the source and drain junctions are used to read the
stored data.

      Indeed, in NMOSFETs biased under accumulation (Fig. 1) so that
a hole accumulation layer 1 exists, a p+/n+  tunnel diode exists at
the source 2 and drain 3 (1).  The reverse bias tunnel current 4,5
through these diodes is very sensitive to the electric field in the
gate-oxide around the drain and source junctions (2).  If electrons
are injected above either the source or drain junction, part of them
are trapped in the gate oxide 6 and modify the electric field, and
hence the current through the associated tunnel diode.  Therefore,
the presence or absence of electrons in the oxide above the two
source/drain junctions can be used to store 2 bits in each MOSFET.

      The cell is made using the same fabrication steps as for an
ordinary NMOSFET, but the gate insulator must be optimized for
enhanced electron trapping, but low detrapping rate.  Oxide nitride
oxide (3) may be used.

      Fig. 2 shows the two bits of the cell under typical operating
conditions.

      During WRITE (Figs. 2a, 2b), hot-electrons are heated and
injected into the oxide on the cell side on which a high voltage is
applied.  The other half of the NMOSFET is unaffected by these
biasing conditions.  The injected electrons modify the electric field
only around the injecting junction.

      During READ of the data (Figs. 2c, 2d), a negative gate voltage
and reverse (positive) junction voltage are applied on the selected
half-device, so that a band to band tunnel current flows from the n+
zone to the substrate.  Since this current is very sensitive to the
electric field configuration only around the junction, its value
indicates whether electrons have been injected in the half-cell or
not, hence the state of the stored bit.  During readout, both the
gate and drain voltages should be kept to the smallest value
necessary to obtain a sufficient readout current (necessary to
discharge parasitic capacitors, hence achieve sufficient speed), but
to avoid electron detrapping or hole injection during the readout
process, which would destroy the stored data (see below).

     ...