Browse Prior Art Database

CMOS Well Structure for Decreasing Soft Error Rate

IP.com Disclosure Number: IPCOM000110190D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Chappell, BA: AUTHOR [+4]

Abstract

Disclosed in this article is a method to fabricate CMOS well structures that would reduce collection of radiation-induced charges in SRAM-like CMOS latches, and hence improve on soft error rate of the circuit.

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This is the abbreviated version, containing approximately 52% of the total text.

CMOS Well Structure for Decreasing Soft Error Rate

       Disclosed in this article is a method to fabricate CMOS
well structures that would reduce collection of radiation-induced
charges in SRAM-like CMOS latches, and hence improve on soft error
rate of the circuit.

      As dimensions shrink, CMOS latches are more susceptible to
radiation-induced soft errors.  While earlier generations were
insensitive to SER (1), an estimate of the SER exposure of the 4 Mb
generation SRAM latch shows that both the 6-device and the thin film
cells would be extremely vulnerable to alpha-particle-induced SER
(certainly to cosmic rays as well).  The reason for the exposure is
that the standby capacitance in the cell is so small, that less than
about 15 fC of minority charge collection is sufficient to switch it.
An alpha particle track can contain 15 fC in less than 1 um of its
length, and this charge can be delivered extremely fast via
funneling, typically in less than 50 ps.  Since collection is fast,
it does not matter that the transistors can be turned on to restore
the original state.  To decrease the SER exposure, one must shorten
the track length that can funnel into the nodes.

      A scheme that accomplishes this with a simple process change is
shown in the figure.  The N+ region biased to Vdd reduces charge
collection on the drains from both the p- and the n-well.  In the
p-well minority carriers are electrons; thus, the N+ region acts like
a sink competing with the N+ drain for the minority carriers.  This
reduces the charge reaching the drain in both the funneling mode and
the diffused mode.  In th...