Browse Prior Art Database

Test Methodology for Cards Including Programmable Logic

IP.com Disclosure Number: IPCOM000110253D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 43K

Publishing Venue

IBM

Related People

Badaoui, M: AUTHOR [+4]

Abstract

Disclosed is a methodology that allows manufacturing test of cards including programmable logic with algorithmic-generated test vectors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Test Methodology for Cards Including Programmable Logic

       Disclosed is a methodology that allows manufacturing test
of cards including programmable logic with algorithmic-generated test
vectors.

      Programmable logic allows a great flexibility by permitting the
designer to change the logic by micro-code change.  Unfortunately,
such a logic is erased by a power cut.  This means that a card with
programmable logic will be put on the tester as a virgin logic card,
the reason being that in most cases the logic is programmed by
circuitry situated on another card.

      For cards where the test patterns are automatically generated
test vectors generated on a given design, there is no way to test.
The structure must be loaded first, before thinking of applying any
test pattern measuring card response.

      The method (see figure) is based on the fact that all
programmable logic can be tested by applying chip logic information
on some of the chip IOs.  Those IOs depend on the chip manufacturer.
The logic information vectors can be treated as test vectors, and the
handshaking required by the chip can be treated as an output to be
monitored by the tester.

      This method can be used for any type of programmable logic.
Test vectors can be automatically generated, or can even be
functional patterns.