Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High Coverage Self Test

IP.com Disclosure Number: IPCOM000110254D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 30K

Publishing Venue

IBM

Related People

Diebold, U: AUTHOR [+6]

Abstract

Self-testing of a logic chip is carried out using a pseudo-random pattern generator (PRPG) to produce test patterns for testing the logic chains in the chip and a multiple input signature register (MISR) connected to the output of the logic chains for capturing a signature representative of the chip. Comparison of the produced signature with the expected signature allows determining whether there are any errors in the chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

High Coverage Self Test

       Self-testing of a logic chip is carried out using a
pseudo-random pattern generator (PRPG) to produce test patterns for
testing the logic chains in the chip and a multiple input signature
register (MISR) connected to the output of the logic chains for
capturing a signature representative of the chip.  Comparison of the
produced signature with the expected signature allows determining
whether there are any errors in the chip.

      As shown in the figure, the test patterns from the PRPG being
input to the logic chains can be further mixed in XOR gates with
values tapped from the MISR.  This has the effect of increasing the
variety of test patterns supplied to the chip and thus the test
coverage.