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Selective Single Bit Error Correction for Micro-control Words

IP.com Disclosure Number: IPCOM000110263D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Hoover, RD: AUTHOR [+2]

Abstract

This article describes a hardware scheme to selectively recover from single-bit errors (SBE) when detected on micro-control words. This is accomplished by encoding additional information in the Error Correction Code (ECC) check bits of the micro-control words.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Selective Single Bit Error Correction for Micro-control Words

       This article describes a hardware scheme to selectively
recover from single-bit errors (SBE) when detected on micro-control
words.  This is accomplished by encoding additional information in
the Error Correction Code (ECC) check bits of the micro-control
words.

      The processor contains SRAM for 8K micro-control words.  This
area is called Control Store (CS).  Control store is loaded from main
storage at IPL time.  Micro-control words may also fetch additional
control words from main storage during normal execution and replace
(overlay) existing control words within CS.  Stored with each control
word in CS are 9 bits of error correction code.  This ECC is a
general single-bit correct double-bit detect error correction code.

      This invention is used to selectively choose not to recover
from a detected SBE.  This invention will provide a method of
selecting on an individual control word basis under control of the
micro-program whether to recover from an SBE or to report a machine
check.

      Each control word (0:55 data bits, 3 parity bits, unrecoverable
bit) is stored within a doubleword (8 bytes) of data in main storage.
The format is as follows:
  Unrecoverable Bit  loaded from MS(0).  ('1'B indicates
unrecoverable) MS(1:2) Reserved.
  CS Parity bit 0    loaded from MS(3).
  CS Parity bit 1    loaded from MS(4).
  CS Data(0:50)      loaded from MS(5:55).
                                 MS(56) Reserved.
  CS Parity bit 2    loaded from MS(57).
                                 MS(58) Reserved.
  CS Data(51:55...