Browse Prior Art Database

High Performance Priority External Interrupt Mechanism

IP.com Disclosure Number: IPCOM000110264D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Shippy, DJ: AUTHOR [+2]

Abstract

This article provides a high performance external interrupt mechanism with a hardware high priority detect, priority mask, and a minimal set of single-cycle instructions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Performance Priority External Interrupt Mechanism

       This article provides a high performance external
interrupt mechanism with a hardware high priority detect, priority
mask, and a minimal set of single-cycle instructions.

      The figure shows the external interrupt mechanism which is
located in the Storage Control Unit (SCU) of a multi-chip
super-scalar reduced instruction set processor.  The primary hardware
functions of the external interrupt mechanism are the Interrupt Level
Control Register (ILCR), the Pending External Interrupt Source
registers (PEIS0, PEIS1), the leading zero detect logic, and the
prioritized mask.  External interrupts can be activated from several
sources: I/O devices via the System I/O (SIO) Bus, interval timer
(DEC), Early Power Off Warning (EPOW), and memory errors (MEEB).
Interrupts are queued as pending in the 64 bits of the PEIS
registers.  An interrupt level may be one of 64 levels (0-63).  Level
0 is the most favored level, and level 64 is the least favored level.
The leading zero detect logic indicates the highest pending
interrupt, and this is loaded in the Pending Interrupt Level (PIL)
field of the ILCR register.  The Current Interrupt Level (CIL) field
of the ILCR is used to mask off interrupts which are less favored
than the value in the CIL field.  This is achieved in hardware by
comparing the CIL field with the PIL field and only activating the
external interrupt signal (EXT_INT) to the processor Icache Unit
(ICU) when the PIL field is less than the CIL field.  When the
EXT_INT signal is activated, the ICU breaks from its current
instruction stream and branches...