Browse Prior Art Database

Simulation of Timing Measurements with State Machine Rules

IP.com Disclosure Number: IPCOM000110265D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Ashley, CL: AUTHOR [+2]

Abstract

Disclosed is a program for measuring simulation delay timings through the application of rules describing a state machine model, to be used for the analysis or verification of simulation timings for circuits at a chip, card, or system level. A rules language is developed for the definition of timing requirements, structured around this model. The timing state machine model is guided to perform a timing calculation through a combination of signal transitions and concurrent Boolean states.

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Simulation of Timing Measurements with State Machine Rules

       Disclosed is a program for measuring simulation delay
timings through the application of rules describing a state machine
model, to be used for the analysis or verification of simulation
timings for circuits at a chip, card, or system level.  A rules
language is developed for the definition of timing requirements,
structured around this model.  The timing state machine model is
guided to perform a timing calculation through a combination of
signal transitions and concurrent Boolean states.

      The movement between states in the program is governed by the
occurrence of signal transitions that are defined by a timing rule.
As illustrated in the state diagram of the figure, these transitions,
such as PRESTART can be qualified by signal states, such as WHILE,
which must be concurrent for the transition to be valid for movement
to the next state of the program.  Multiple transition conditions
define alternate means to move to the next state.

      WHILE statements are optional.  One or more WHILE statements
can follow another statement, such as PRESTART.  Each WHILE statement
applies additional constraints on the preceding statement, naming a
signal and a desired state which must be valid for the condition of
the preceding statement to be valid.

      The PRESTART statement is an optional part of a timing
parameter rule, which is used whenever a timing specification
involves prior conditions before a particular parameter measure...