Browse Prior Art Database

High Capacity DASD Type Storage

IP.com Disclosure Number: IPCOM000110313D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 96K

Publishing Venue

IBM

Related People

Gueret, P: AUTHOR

Abstract

Described is a scheme for high-capacity direct access type storage, i.e., with a bitsize of less than 100 nm, of which the figure shows a diagrammatic view. In a holder 1 there are mounted a plurality of mutually insulated metallic plates 2...5 each connectable via a resistor 6...9 and a multiple switch 10 to a common voltage source 11. Each of the plates 2...5 carries an electrically conducting small dot 12...15 on its surface facing downward in the figure. For addressing, holder 1 can be translated horizontally over a large area, a page, by means of a piezodrive 16, so that each dot 12...15 can address all points contained within the area of one page.

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High Capacity DASD Type Storage

       Described is a scheme for high-capacity direct access
type storage, i.e., with a bitsize of less than 100 nm, of which the
figure shows a diagrammatic view.  In a holder 1 there are mounted a
plurality of mutually insulated metallic plates 2...5 each
connectable via a resistor 6...9 and a multiple switch 10 to a common
voltage source 11.  Each of the plates 2...5 carries an electrically
conducting small dot 12...15 on its surface facing downward in the
figure.  For addressing, holder 1 can be translated horizontally over
a large area, a page, by means of a piezodrive 16, so that each dot
12...15 can address all points contained within the area of one page.

      The dots 12...15 cooperate with a storage medium 17 comprising
a metallic substrate 18 with a layer 19 of silicon nitride deposited
thereon, which, in turn, carries a layer 20 of silicon dioxide and a
final layer 21 of silicon.  The substrate 18 can be grounded by
operating a switch 22.

      For writing information, the storage medium 17 is approached to
the metal plates 2...3 and their dots 12...15, and switch 22 is
closed.  The metal plates 2...5 to be addressed are connected via
switch 10 to voltage source 11 which has a large enough negative
voltage to cause a current to flow from the addressed dots 12...15
through the silicon-based layers 19...21 to the substrate 18.  When
switch 10 is opened again, the current ceases to flow, and charges
remain store...