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Browse Prior Art Database

Algorithm for Logic Block Power Level Optimization Based on Timing Slack

IP.com Disclosure Number: IPCOM000110321D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 9 page(s) / 426K

Publishing Venue

IBM

Related People

Borkenhagen, JM: AUTHOR [+5]

Abstract

A computer algorithm for automatically selecting power levels of logic blocks in ASIC designs is disclosed. The computer algorithm provides an optimized ASIC timing solution with minimum area and power usage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 17% of the total text.

Algorithm for Logic Block Power Level Optimization Based on Timing Slack

       A computer algorithm for automatically selecting power
levels of logic blocks in ASIC designs is disclosed.  The computer
algorithm provides an optimized ASIC timing solution with minimum
area and power usage.

      The logic-block power-level optimization algorithm works by
taking a given design and performing timing analysis and area
analysis to see if performance and area requirements are met.  If the
timing or area requirements of the design are not met, the power
level of some blocks will be changed.  A unique method is used to
determine which of the blocks are the best candidates for powering up
or down.  The selected blocks will then be repowered.  Timing and
area analysis are repeated to see if the requirements are met.  This
iteration between analysis and repowering continues until the
requirements are met or other limits are reached.  Fig. 1 displays a
high-level view of the block power-level optimization algorithm.

      The unique part of this repowering algorithm is the manner in
which logic blocks are selected for repowering.  Two block selection
criteria (BSC) are used, one for selecting blocks which should have
increased power (power up) and one for selecting blocks which could
be powered down.

      In an effort to meet the design timing and area goals, the BSC
for powering up (BSCpu) attempts to identify those logic blocks which
have the most influence over the timing of critical logic paths.
Conversely, the BSC for powering down (BSCpd) allows the maximum
number of blocks to be powered down without creating critical paths.

      Both BSCpu and BSCpd scores are calculated for each logic block
in the design.  The scores are used to rank the blocks for
repowering.  The blocks with relatively high BSCpu scores are
considered the best candidates for powering up, while the blocks with
the highest BSCpd scores will be selected for powering down.  A BSCpu
score of zero indicates that the block should not be powered up, and
a BSCpd score of zero means that the block should not be powered
down.

      Calculating the influence of a particular block on the timing
of the design can be very complex.  The influence of a block can be
defined in many ways and it depends on many variables in the design
structure and timing.  Some of the most important factors governing
the influence of a block are: How many critical paths go through the
block?, How critical are those paths (as compared to other paths in
the design)? and How good is the transition rate on the signal at
this point in the logic?.

      The following lines define some of the specific factors which
may be used to determine the influence of a particular block on the
timing of the design:
BLK_SLACK              Blk_slack is a numerical value representing
the worst timing slack (margin) on any path which goes through the
block in question.
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