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Delay Circuit using Delay Locked Loop

IP.com Disclosure Number: IPCOM000110324D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 5 page(s) / 195K

Publishing Venue

IBM

Related People

Strom, JD: AUTHOR

Abstract

System design requires that the accuracy of delay paths and between clock signals be minimized over process, temperature, and power supply variations. A method of compensating an electrical delay path is disclosed. The technique can be used to generate accurate delayed clock edges as well as accurate logic delays. The method described can be fully implemented on an integrated circuit.

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Delay Circuit using Delay Locked Loop

       System design requires that the accuracy of delay paths
and between clock signals be minimized over process, temperature, and
power supply variations.  A method of compensating an electrical
delay path is disclosed.  The technique can be used to generate
accurate delayed clock edges as well as accurate logic delays.  The
method described can be fully implemented on an integrated circuit.

      This circuit provides a method to generate differential clocks
as well as an accurate delay path which are any fraction of the input
cycle, depending on the number of Variable Delay (N) circuits used
and the type of Phase Detector (X) used.

      In Fig. 1, N Variable Delay circuits are used along with an X
Degree Phase Detector to generate a delay of X/N per Variable Delay
book.  The differential reference voltage generated by the Phase
Detector and Charge Pump can be fed to Variable Delay books which are
not included inside the loop of the Phase Detector.  A Variable Delay
book which receives the differential reference voltage can then be
inserted between logic blocks for timing purposes.

      Fig. 2 shows a implementation of this concept in which N=2 and
X=90 degrees.  Rather than delaying a logic signal, the delayed input
to the Phase Detector was delayed by two additional Variable Delay
circuits.  This allows for a delay measurement to be made at module
level of 180 degrees to verify the circuit.  The reference input
arrives at inputs A0 and A1 in Fig. 2.  Circuit ZS00 provides a
resistive termination and level shifting.  The output of ZS00 circuit
then drives the Quadrature Detector, output buffer ZS90 and Variable
Delay Circuit ZS80.  Another Variable Delay circuit ZS81 is cascaded
on to the output of ZS80 through emitter follower ZSE0.  Emitter
follower ZSE2 level shifts the output of the two cascaded Variable
Delay circuits and drives the delayed input to the Quadrature
Detector.  It is also possible to use other types of Phase Detectors
than the Quadrature Detector.

      The delayed signal is then fed to a Quadrature Detector which
generates equal up and down pulses for two signals which are ninety
degrees out of phase.  The other input to the Quadrature Detector is
the reference signal.  The output of the Quadrature Detector drives a
Charge Pump.  The Charge Pump filters the Quadrature Detector output
and provides a DC voltage to each of the Variable Delay circuits
which adjusts the delay of the Variable Delay Circuits until the
difference between the reference input and the delayed signal is 90
degrees.  Note t...