Browse Prior Art Database

Parallel Port Addressing for Personal Computers

IP.com Disclosure Number: IPCOM000110371D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Cohen, MC: AUTHOR [+2]

Abstract

Described is a software implementation for personal computer (PC) systems to provide access to an extended set of parallel port registers without disrupting existing parallel port register definitions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Parallel Port Addressing for Personal Computers

       Described is a software implementation for personal
computer (PC) systems to provide access to an extended set of
parallel port registers without disrupting existing parallel port
register definitions.

      The technique used in the implementation increases the
accessible parallel port register range and maintains compatibility
with existing port implementations.  In prior art, a parallel port
interface had only eight input/output (I/O) register addresses
reserved by the architecture in system space.  In order to provide
enhanced functional capabilities, such as bus master mode parallel
port operations, additional I/O accessible registers would be
required.  Also, a method was needed to extend the standard
eight-byte register set without requiring additional I/O space to be
reserved by the system.  Above all, the design must ensure that
complete compatibility with the existing parallel port
implementations is maintained.  The concept described herein provides
a compatible register definition using parallel port addresses
Base+6/ Base+7 that enables register stack sub-addressing.

      Fig. 1 lists the prior-art standard parallel-port I/O register
assignments.
        ADDRESS     R/W     DEFINITION
        [[[[[[[     [[[     [[[[[[[[[[
        Base + 0    R/W     Parallel Data Register (PDR)
        Base + 1    R       Device Status Register (DSR)
        Base + 2    R/W     Device Control Register (DCR)
        Base + 3    R/W     Interface Control Register (ICR)
        Base + 4    R       Interface Status Register (ISR)
        Base + 5    R/W     Strobe Timer Register (STR)
        Base + 6    *       Reserved and set to B'1's
        Base + 7    *       Reserved and set to B'1's
                        Fig. 1

      Fig. 2 lists the new parallel port I/O register assignments
with the Base+6 and the Base+7...