Browse Prior Art Database

Mechanism for Reducing Component Module Pin Count in Personal Computers

IP.com Disclosure Number: IPCOM000110373D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 127K

Publishing Venue

IBM

Related People

Clarke, GL: AUTHOR [+5]

Abstract

Described is an architectural implementation that reduces the component module pin count in personal computers so as to increase the addressing capability of a system memory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mechanism for Reducing Component Module Pin Count in Personal Computers

       Described is an architectural implementation that reduces
the component module pin count in personal computers so as to
increase the addressing capability of a system memory.

      In prior art, the design of the random-access memory (RAM)
interfaced the input of an external extended memory directly and
would be driven by a very large-scale integrated (VLSI) device.  This
design was practical only if the VLSI device had a sufficient number
of access pins on the module.  Typically, a full implementation
required 16 pins for the address bits to enable a matrix of 64K x 8,
one read and one write, one buffer enable and one buffer direction
pin for a total of 20 pins.  The concept described herein provides a
method whereby, through architectural implementation, the number of
pins is reduced to only two pins.

      Fig. 1 shows the logic diagram interface for the new RAM
module, called NOVRAM.  The NOVRAM is accessed using three
input/output (I/O) operations.  Writing to I/O address 74 latches
data bits 0 through 7 as the lower 8 address bits for the NOVRAM.
The I/O WRITE to address 75 generates address bits 8 through 15 in
the same manner.  After the NOVRAM address has been established, an
I/O WRITE to address 76 stores the data byte in the cell array
selected by the previously written address bits 0 through 15.  To
read data from the NOVRAM, an I/O READ to address 76 must be
performed.  This places the byte contained in the storage elements
previously selected onto the data bus.

      Two new signals are generated by the circuit: +NOVRAM 1 and
+NOVRAM 2.  Both signals are encoded decodes of addresses 74 through
76.  Only the +NOVRAM 1 is high when address 74 is active, and only
the +NOVRAM 2 is high when address 75 is active.  Both signals are
high when address 76 is valid.  The other four signals; -ENABLE
BUFFER, +DIRECTION, -I/O READ and -I/O WRITE are not specific to the
NOVRAM interface.  +DIRECTION goes active high when any write
operation, memory or I/O, is decoded from status bits S0 and S1.  The
state of this line determines the direction of the external data
buffer.  Whenever the I/O operation lies within the address range of
most functions, -ENABLE BUFFER goes low to enable the external data
buffer.  -I/O READ or -I/O WRITE go activ...