Browse Prior Art Database

Burst Enable Bit for Floppy Disk Controllers

IP.com Disclosure Number: IPCOM000110375D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Klim, P: AUTHOR [+2]

Abstract

Described is a hardware logic implementation that provides a burst enable bit for floppy disk controllers (FDCs) during direct memory access (DMA) operations as used in personal computer (PC) systems equipped with the Micro Channel* (MC).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 89% of the total text.

Burst Enable Bit for Floppy Disk Controllers

       Described is a hardware logic implementation that
provides a burst enable bit for floppy disk controllers (FDCs) during
direct memory access (DMA) operations as used in personal computer
(PC) systems equipped with the Micro Channel* (MC).

      The concept described herein provides a means whereby the
floppy disk controller is provided a means of preventing the FDC from
operating in burst mode during a DMA operation by utilizing a burst
enable bit.  The burst mode signal to the MC can be disabled by
programming.

      When the first-in, first-out (FIFO) circuitry inside the FDC is
enabled by way of the configured command, the processor will detect
this operation and enable the burst to the MC.  A floppy DMA cycle
automatically asserts burst, indicating that more than one DMA
transfer will take place.  However, it may not be desirable to turn
burst on if a source other than a specific processor already drives
burst onto the MC.  Therefore, a power on system (POS) register bit
has been implemented to override the enable signal received by way of
the FDC configure command.

      The figure shows the architectural logic diagram for the POS
burst enable register.  The POS burst enable register bit may be
accessed when bit 7 in Port 94 is set to zero.  The POS burst enable
register bit may be written to or read from Port 104 where a logic
one of data bit 5 will indicate that burst is disabled.  Upon po...