Browse Prior Art Database

Asynchronous Generation of DRAM Controls from Micro Channel Signals

IP.com Disclosure Number: IPCOM000110384D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 60K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

In some situations, there is a requirement for additional data to determine if a slave device is ready to accept a MICRO CHANNEL* operation. This requirement is specific to the slave and may be architected as such. An example of this is the Translation Control Word (TCW) described in the POWER IO Architecture. In this case, minimum DRAM access delay is desirable because it directly results in a shorter CD_CHRDY = 0 period. In any situation where CD_CHRDY was held low until the data could be retrieved, the minimum DRAM access delay would be most desirable.

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Asynchronous Generation of DRAM Controls from Micro Channel Signals

       In some situations, there is a requirement for additional
data to determine if a slave device is ready to accept a MICRO
CHANNEL* operation.  This requirement is specific to the slave and
may be architected as such.  An example of this is the Translation
Control Word (TCW) described in the POWER IO Architecture.  In this
case, minimum DRAM access delay is desirable because it directly
results in a shorter CD_CHRDY = 0 period.  In any situation where
CD_CHRDY was held low until the data could be retrieved, the minimum
DRAM access delay would be most desirable.

      The DRAM is accessed by RAS (Row Address Select) and CAS
(Column Address Select) signals which generally must be of a minimum
specific pulse width.  CAS usually follows RAS.  The access time of
the DRAM is specified from RAS if CAS is presented less than some
minimum later or from CAS if the minimum is exceeded.  Typical pulse
width constraints are RAS - 80 ns minimum, and CAS - 40 ns minimum.
If the RAS is more than 20 ns before CAS, the typical access time is
35 ns from CAS; otherwise, the access time is 80 ns from RAS.

      Since the timing constraints of the typical DRAM are consistent
with the MICRO CHANNEL specifications for -S0/S1 and -ADL, these
signals can be taken, asynchronously to the slave's internal clock,
from the MicroChannel to control the DRAM.  (For reference: -S0/S1
minimum pulse width is 85 ns,...