Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Multi-processing System Programmable Memory Interleave Apparatus

IP.com Disclosure Number: IPCOM000110397D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 103K

Publishing Venue

IBM

Related People

Shippy, DJ: AUTHOR [+2]

Abstract

This article provides a programmable memory interleave scheme for a multi-processor computer system. This includes the capability for software to select the granularity of the memory interleave as well as the number of memory banks and the size of each memory bank.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Multi-processing System Programmable Memory Interleave Apparatus

       This article provides a programmable memory interleave
scheme for a multi-processor computer system.  This includes the
capability for software to select the granularity of the memory
interleave as well as the number of memory banks and the size of each
memory bank.

      Fig. 1 shows the interleave apparatus which is located within a
CENTRAL MEMORY CONTROL (CMC) unit.  Processors initiate memory
requests via the Processor Bus (PBUS).  Data is transferred to memory
via a standard crossbar switch (Fig. 2) which the CMC unit controls.
In addition, the CMC unit generates the memory address and activates
bank selects to memory banks. In a multi-processor system, memory
data transfers are overlapped when they do not hit in the same bank
of memory.  The primary hardware functions of the interleave
apparatus are as follows.

      The STORAGE CONFIGURATION REGISTER is a register initialized by
software which controls the granularity of the interleave, the bank
ID for each bank, and the memory size for each bank.  The STORAGE
CONFIGURATION REGISTER fields are defined as follows.  The interleave
(INT) field specifies the interleave granularity.  The Bank ID fields
(BID 0, 1, 2, 3) specify the bank ID for memory banks 0 to 3.
The Extent fields (EXT 0, 1, 2, 3) specify the extent size of memory
banks 0 to 3.

      The BANK NUMBER DECODE logic indicates the number of banks
installed.  The...