Browse Prior Art Database

Latching Branch Instruction Signals and Queuing Target Instructions

IP.com Disclosure Number: IPCOM000110406D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Hicks, TN: AUTHOR [+2]

Abstract

Disclosed is a target register queue allowing critical branch timing signals from the fixed point and instruction cache to be latched; as a result, the target instructions are multiplexed the following cycle.

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This is the abbreviated version, containing approximately 95% of the total text.

Latching Branch Instruction Signals and Queuing Target Instructions

       Disclosed is a target register queue allowing critical
branch timing signals from the fixed point and instruction cache to
be latched; as a result, the target instructions are multiplexed the
following cycle.

      Without affecting fixed-point performance, target instructions
of an unresolved FXU branch are dispatched from the ICU and held in
the floating-point target instruction buffers.  This eliminates
critical branch timing signals from the FXU by allowing the floating
point to see the resolution of a pending branch a cycle late.  The
ICU will be dispatching more instructions off the target the same
cycle the FPU sees the latched version of the branch.

      There are four valid target instructions of a branch on the
instruction bus (Tar_On_Ibus = B'1').  The target instructions will
move into the target buffers until the branch is resolved.  The
instructions E, F, G, and H are in the target buffers.

      Conditional instructions are instructions sequentially after an
unresolved branch instruction.  The instructions A, B, C, and D are
tagged as conditional.  When the branch is resolved as taken, they
are cancelled and the target instructions E, F, G, and H are received
from the target buffers.

      The FXU resolves the branch as taken (Fxu_Br_Taken = B'1') and
the target instructions (E, F, G, and H) are mixed into the
instruction prefetch buffers (IPBs).  In th...