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Phase Recovery Techniques using Digital Circuits

IP.com Disclosure Number: IPCOM000110407D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 166K

Publishing Venue

IBM

Related People

Anderson, C: AUTHOR [+2]

Abstract

Disclosed are techniques which may be employed to retime data signals of known frequency but indeterminate phase, using digital circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Phase Recovery Techniques using Digital Circuits

       Disclosed are techniques which may be employed to retime
data signals of known frequency but indeterminate phase, using
digital circuits.

      Phase recovery circuits, such as phaselock loops (PLLs), are
commonly used in optical links, disk interfaces, and chip interfaces
for the purpose of retiming data (1-3).  Often the clock is derived
from the incoming data.  When many data inputs of common frequency
must be retimed on a single chip, it may be desirable to adjust the
phase of each data input so that all inputs may be retimed to the
same clock.  This article describes two delay-align approaches which
may be used to retime data to a local clock using VLSI-compatible
digital circuits.

      The proposed method of phase recovery is shown in Fig. 1.
Input data DIN is to be retimed to local clock +CLK.  The data is
connected to a delay chain consisting of the following elements in
sequence: a variable-delay element, a fixed-delay chain of inverters,
a set of two identical variable-delay elements, and a second
fixed-delay chain of inverters.  Delays are chosen such that the
delay from DA1 to DA2 is always less than two bit intervals, and is
in one bit interval when the variable delays are centered.  The data
at each element within the first fixed-delay chain is sampled in a
register using +CLK.  Transition detectors are employed to locate the
position of any data transitions--Early or Late with respect to
position DA1--captured within the sampled string of data.  This
positional information,  when averaged by a digital filter (4), is
used to control the delay of the data through the first
variable-delay element.  If more samples are "Late" than "Early",
then the delay of the data is decreased; if more samples are "Early"
than "Late", then the delay is increased.  This adjustment of delay
aligns the average position of the transitions within the sampled
data to position DA1.  Similarly, the data at each element within the
second fixed-delay chain is sampled in a register using +CLK;
transition detectors, digital filter, and two variable delays
complete a second feedback loop used to align the average position of
data transitions to position DA2.

      The average position of transitions located on each side of a
single bit interval is actively controlled by the two feedback loops.
Because the delay from DA1 to DS is made to match the delay from DS
to DA2, the appropriate sampling point for retiming the data is
aligned to position DS.  When data from DS is retimed at an
edge-triggered flip-flop using +CLK, it is sampled near the center of
the eye.  Timing is shown in Fig. 2.

      When RESET is asserted, the delay-control output of each
digital filter is forced to near the center of its range.  Phase
acquisition begins when RESET is deasserted....