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Disposable Oxide Sidewall for Lateral Self Alignment in Epitaxial Base, Single Poly, Bipolar Transistors

IP.com Disclosure Number: IPCOM000110415D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Comfort, JH: AUTHOR

Abstract

The use of a disposable oxide sidewall to self-align the intrinsic and extrinsic base regions of an epitaxial base transistor is proposed which allows one to form a shallow base contact with a low annealing cycle consistent with narrow basewidth fabrication.

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Disposable Oxide Sidewall for Lateral Self Alignment in Epitaxial Base, Single Poly, Bipolar Transistors

       The use of a disposable oxide sidewall to self-align the
intrinsic and extrinsic base regions of an epitaxial base transistor
is proposed which allows one to form a shallow base contact with a
low annealing cycle consistent  with narrow basewidth fabrication.

      In the established single-poly bipolar technology a
nitride/oxide stack is used to define the intrinsic base and emitter
regions of a bipolar transistor using selective oxidation (*).  A
polysilicon sidewall is formed on the nitride stack to space the
extrinsic base implants away from the emitter opening.  Polysilicon
is used so that a selective silicon etch  may be used for subsequent
removal without etching of exposed field oxide.  One must form this
sidewall after the selective oxidation so that no etching of the
extrinsic base region occurs during sidewall removal.  This requires
that the implantation occur through the isolation oxide and thus at
relatively high energies.  The resultant junction depth is roughly
300-400 nm and an annealing cycle of roughly 880oC for 20 minutes is
required. This thermal budget is inconsistent with the fabrication
of epitaxial base transistors with final basewidths between 10 and
100 nm.

      In an epitaxial base technology, a thin polysilicon layer may
be deposited over the field oxide at the same time as the active
layer base deposition.  Thus, the entire wafer surface is...