Browse Prior Art Database

Time Division Multiplexed Vectored Interrupt

IP.com Disclosure Number: IPCOM000110423D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 110K

Publishing Venue

IBM

Related People

Andrews, LP: AUTHOR [+5]

Abstract

This article describes a time division multiplexed vectored interrupt (TDMVI) which provides equal priority to vectored interrupt requesting devices with few signal lines.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Time Division Multiplexed Vectored Interrupt

       This article describes a time division multiplexed
vectored interrupt (TDMVI) which provides equal priority to vectored
interrupt requesting devices with few signal lines.

      Interrupt lines can be configured in different ways.  One
technique is to have the interrupt request line dotted together and
the interrupt acknowledge line daisy chained (Fig. 1).  Another
technique is to have the interrupt request lines daisy chained and
the interrupt acknowledge lines dotted together (Fig. 2).  These two
techniques suffer from position-dependent prioritization.  Other
techniques require the use of an interrupt prioritizer (Fig. 3).
This technique offers some flexibility, but requires additional logic
and additional signal lines for implementation.

      An illustration of the TDMVI disclosed herein is shown in Fig.
4.  The system clock is already available on the bus, so this does
not represent an additional signal line.  The SYNC signal is used to
synchronize an internal counter inside every device on the bus.  This
internal counter is clocked by the system clock.  The contents of the
counter is compared with each device's physical address.  The
physical address actually corresponds to a time slot indicated by the
counter.  If the physical address matches the contents of the
counter, then the current time slot belongs to that device.  At this
time the device is allowed to request an interrupt by assert...