Browse Prior Art Database

Cache Failure Analysis

IP.com Disclosure Number: IPCOM000110456D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

OLeary, B: AUTHOR [+2]

Abstract

In today's hardware caches which are used to improve the performance of accessing data, the cache arrays can fail intermittently (soft) or solidly (hard). There are recovery mechanisms to bypass the effects of such errors by deleting a cache line, removing a cache compartment or relocating addresses within the cache arrays.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 81% of the total text.

Cache Failure Analysis

      In today's hardware caches which are used to improve the
performance of accessing data, the cache arrays can fail
intermittently (soft) or solidly (hard).  There are recovery
mechanisms to bypass the effects of such errors by deleting a cache
line, removing a cache compartment or relocating addresses within the
cache arrays.

      Capturing the characteristics of cache array failure modes
provides the ability to correct potential problems with technology,
process, packaging or the hardware implementation.

      This design describes the data capture requirements for the
hardware design as well as a service processor algorithm to extract
data at the time of failure.  In-line service processor analysis, as
well as post-process algorithms, can be accomplished against logged
cache failure data.

      Hardware to capture a fully qualified cache address with
directory pointers is the major design item along with a matrix to
map captured data to array and cell locations.  These requirements
are beyond what is necessary to manage deletion of a cache line.
With this captured data, the service processor algorithm will use the
time stamp and characteristics of the previous failure to distinguish
not only soft and hard failures, but the physical failure signature.
These signatures will be categorized by effected chip, cell location,
bit line, word line or chip kill.  Post processing the failure
profiles against projected piece part fa...