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Fully Self Aligned Extrinsic Base Requiring No Additional Lithography for Epitaxial Base Processes

IP.com Disclosure Number: IPCOM000110484D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

Bronner, G: AUTHOR [+4]

Abstract

Disclosed is a process for obtaining a self-aligned extrinsic base in an epitaxial-base bipolar process with no additional lithography. The process self-aligns the extrinsic base to the edge of the field oxide region, avoiding implantation and any annealing steps following base deposition. This process can be implemented both with Recessed Oxide isolation (ROX) and Shallow Trench isolation (ST).

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Fully Self Aligned Extrinsic Base Requiring No Additional Lithography for Epitaxial Base Processes

      Disclosed is a process for obtaining a self-aligned extrinsic
base in an epitaxial-base bipolar process with no additional
lithography.  The process self-aligns the extrinsic base to the edge
of the field oxide region, avoiding implantation and any annealing
steps following base deposition.  This process can be implemented
both with Recessed Oxide isolation (ROX) and Shallow Trench isolation
(ST).

      The fabrication sequence is the following.  After patterning
the pad oxide and nitride layers prior to the silicon etch, the
silicon is partially recessed (to ~ 200 nm) as illustrated in Fig.
1(a).  The resist is stripped, a heavily boron-doped low temperature
oxide is deposited and a disposable sidewall is formed (Fig. 1(b)).
A diffusion step such as a Rapid Thermal Anneal step at 1050~C then
drives boron into the silicon.  The diffusion time and temperatures
can be adjusted to select the width and doping of the extrinsic base
region.  The surface concentration is given by the boron solid
solubility at the anneal temperature chosen.  The sidewall is then
removed and the etch of the silicon can be completed using nitride as
a mask (Fig. 1(c)).  A thermal oxidation follows for ROX and oxide
deposition follows for ST isolation (Fig. 1(d)).

      Alternatively, one could use a thin, supersaturated Low
Temperature Epitaxial Silicon layer.  Out diffusion...