Browse Prior Art Database

Low Cost Frame Buffer for Memory Addressing

IP.com Disclosure Number: IPCOM000110501D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Arroyo, RX: AUTHOR [+3]

Abstract

Disclosed is a method for providing low-cost frame buffer design for large videoscreen resolutions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 60% of the total text.

Low Cost Frame Buffer for Memory Addressing

       Disclosed is a method for providing low-cost frame buffer
design for large videoscreen resolutions.

      Large video screen resolutions, such as 1280 x 1024, require a
large amount of pixel data to implement.  With eight bits per pixel
approximately 2 megabytes of data are required.  Only 1.3 megabytes
of VRAM may be utilized if organized with a five pixel read/write
interface.  However, a five-pixel interface requires a higher cost
digital to analog converter.  The method disclosed herein first
divides a 1280 pixel wide display into five sections of 256 pixels
each, referred to as sections A through E.

      A frame buffer 10 is provided utilizing five 256K x 4 VRAM
devices 12 with split register serial transfer capability, as
depicted in the figure.  A five byte wide data path is provided to
the VRAM from the VRAM controller and four bytes are written into the
VRAM device 12 utilizing various four-byte combinations from the five
byte wide data path.  For example, the A section of a digital screen
is written into banks 1-4 of VRAM device 12.  The B section is
written to banks 0 and 2-4 and the C and D sections are written as
illustrated.

      For the first four sections of data, the column address for all
accesses to the VRAM are identical.  When the fifth section is
written to the unused areas of the VRAMs, it will require a separate
column address to each bank of the VRAMs.  This is due to...