Browse Prior Art Database

Fast Data Access of Drams by Utilizing a Queued Memory Command Buffer

IP.com Disclosure Number: IPCOM000110516D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Carnevale, MJ: AUTHOR [+3]

Abstract

A method for accessing DRAMs utilizing a queued memory command buffer is disclosed. Random processor reads and writes to DRAMs may or may not hit the same page (column address). When random processor reads and writes do hit the same page, the access time is greatly reduced because the row address does not have to be presented to the DRAMs. The following describes a technique for determining if the next memory access is on the same page as the last (current) memory access.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fast Data Access of Drams by Utilizing a Queued Memory Command Buffer

       A method for accessing DRAMs utilizing a queued memory
command buffer is disclosed.  Random processor reads and writes to
DRAMs may or may not hit the same page (column address).  When random
processor reads and writes do hit the same page, the access time is
greatly reduced because the row address does not have to be presented
to the DRAMs.  The following describes a technique for determining if
the next memory access is on the same page as the last (current)
memory access.

      This article only addresses random processor reads and writes.
Processor reads to fill a cache page are always on page boundaries
and, therefore, to assume the next processor read will hit the same
page as the last one is not a problem.  CISC processors generally
access memory (access in this disclosure means reads or writes)
around 50 percent of the time.  Although stack operations generally
hit the same page as the last memory access, there are many
instances, like memory to memory block moves, that do not.  The
optimal way to decide if the next memory access is going to hit the
same page as the last access is to look ahead to the next instruction
that accesses memory and, based on that instruction's memory address,
make a decision on staying or not staying in page mode.

      Fig. 1 illustrates a typical DRAM access.  The row address
strobe (RAS) goes low when the row address is valid on the address
bus and then, after a certain length of time (address hold time), the
address bus switches to the column address and the column address
strobe (CAS) is driven low.  Both RAS and CAS return to the inactive
state when the memory access is complete.  Fig. 2 shows two
consecutive memory accesses to the same page (row address is the
same).  Because the row address does not have to be presented to the
DRAM, the second access time can be done in one cycle (a cycle has to
be greater than the access time from Column Address Valid and access
time from CAS, but it can be less than access time from RAS).  The
advantages of being able to keep the DRAM in page mode are obvious.
The problems are deciding whether or not to stay in page mode and
keeping the memory controller busy enough to access memory every
cycle.

      One solution to these problems would be to queue the memory
operations in a buffer.  Fig. 3 shows a system without a memory
queue.  The memory controller in Fig. 3 receives an instruction from
the instruction dispatching unit (in this example, in...