Browse Prior Art Database

Principles for Designing a Series of Three Dimensional Graphics Adapters

IP.com Disclosure Number: IPCOM000110560D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 191K

Publishing Venue

IBM

Related People

Luken, WL: AUTHOR

Abstract

A systematic framework for designing a family of graphics adapters for a computer workstation is disclosed. A graphics adapter is a set of electronic circuits which produce analog video signals under the control of a host processor. The analog video signals produce a rectangular pattern of dots or pixels on a cathode ray tube (CRT). Although several specific graphics adapter designs are presented as parts of this invention, the principal purpose of this invention is to establish the systematic relationships between these graphics adapters. Description of the apparatus

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This is the abbreviated version, containing approximately 38% of the total text.

Principles for Designing a Series of Three Dimensional Graphics Adapters

       A systematic framework for designing a family of graphics
adapters for a computer workstation is disclosed.  A graphics adapter
is a  set of electronic circuits which produce analog video signals
under the control of a host processor.  The analog video signals
produce a rectangular pattern of dots or pixels on a cathode ray tube
(CRT).  Although several specific graphics adapter designs are
presented as parts of this invention, the principal purpose of this
invention is to establish the systematic relationships between these
graphics adapters.
Description of the apparatus

      The apparatus resulting from this invention consists of a set
of graphics adapters.  Each of these adapters includes the following
basic components:
1.  A printed circuit board providing physical support for the
remaining components as well as supporting appropriate electrical
connections between these components and the host bus.
2.  A bus interface circuit (BIC) providing electrical connection
between the host bus and subsequent components identified below.
3.  A frame buffer (FB) consisting of digital memory in sufficient
quantity to record all of the information in a rectangular block of
dots or pixels.
4.  Digital to analog converters (DACs), capable of reading the frame
buffer memory and producing analog video signals for refreshing the
screen of a CRT.
5.  Pixel storage unit (PSU).  This is a circuit capable of taking
pixel data values from the bus interface circuit and storing them in
appropriate addresses within the frame buffer memory.

      In addition to these basic parts, each graphics adapter
contains one or more of the following components:
1.  Depth buffer (Z-buff).  This circuit contains memory sufficient
for storing a depth value (Z) for each pixel value defined in the
frame buffer memory.
2.  Scan line processor (SLP).  This circuit must be capable of
transferring pixel data from the bus interface circuit to a pixel
storage unit unchanged.  This circuit must also be capable of
processing scan line data defined by an initial row (y), column (x),
depth (z), and color (r,g,b), number of columns (nx), and the
derivatives of y, z, r, g, and b with respect to x.
3.  Triangle area fill processor (TAFP).  This circuit must be
capable of transferring pixel data or scan-line data from the bus
interface circuit to a scan line processor unchanged.  This circuit
must also be capable of processing shaded triangle data such as that
defined by the Gonzalez-Liang area fill algorithm (US Patent
4,805,116).  The results of this processing may be represented by
scan-line data as recognized by the scan-line processor.
4.  Triangle set-up processor (TSP).  This circuit must be capable of
transferring pixel data, scan-line data, or triangle area fill data
from the bus interface circuit to a triangle area fill processor
unchanged.  In addition, this circuit...