Browse Prior Art Database

Multiple Micro Channels

IP.com Disclosure Number: IPCOM000110570D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Bealkowski, R: AUTHOR [+2]

Abstract

This article describes an apparatus and method for implementing multiple MICRO CHANNEL* buses within a computer system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiple Micro Channels

       This article describes an apparatus and method for
implementing multiple MICRO CHANNEL* buses within a computer system.

      In prior-art computer systems a single MICRO CHANNEL bus is
supported.  The MICRO CHANNEL bus provides up to eight slots.  These
slots provide the means by which feature adapters can be incorporated
into the system.  A feature adapter plugs into a MICRO CHANNEL slot
providing an electrical and mechanical coupling of the feature
adapter and the MICRO CHANNEL bus.  Characteristics of the MICRO
CHANNEL bus restrict the total amount of slots to a maximum of eight.
It is desirable to extend the amount of slots, hence, feature
adapters, that can be supported in a single computer system.

      A multiple MICRO CHANNEL system is achieved by defining a
plurality of MICRO CHANNEL segments.  Referring to Fig. 1, there is
shown a block diagram of a system with multiple MICRO CHANNEL buses.
The processor 10, memory control 12, system memory 14 and system bus
32 are well known elements of a computer system.  For convenience,
two MICRO CHANNEL controllers are shown; MICRO CHANNEL controller #1
16 and MICRO CHANNEL controller #2 18.  Each MICRO CHANNEL bus has
its corresponding slots, slot 1 24 through slot 7 26 on MICRO CHANNEL
#1 38 and slot 1 28 through slot 7 30 on MICRO CHANNEL #2 40.
The MICRO CHANNEL segments are connected to each other through the
central map and decoder 20 and the fast exchange logic 22.  The
central map and decoder provides a MICRO CHANNEL controller #1 select
34, a MICRO CHANNEL controller #2 select 36 and a control interface
42.  The central map and decoder 20 logic and the fast exchange logic
22 present a load to each MICRO CHANNEL controller limiting each
segment to up to seven slots.

      The central map and decoder 20 determines how to route bus
cycles.  A bus cycle can originate on...