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Improved Built-in Self Test Method for Computer Test Gate Functions

IP.com Disclosure Number: IPCOM000110572D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 128K

Publishing Venue

IBM

Related People

Cook, DC: AUTHOR

Abstract

Described is a hardware improvement for level-sensitive scan design (LSSD) devices which incorporates an improved built-in self test (BIST) device that reduces the test time and increases test coverage of computer test gate functions.

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This is the abbreviated version, containing approximately 52% of the total text.

Improved Built-in Self Test Method for Computer Test Gate Functions

       Described is a hardware improvement for level-sensitive
scan design (LSSD) devices which incorporates an improved built-in
self test (BIST) device that reduces the test time and increases test
coverage of computer test gate functions.

      Typically, the testing of logic gate functions involves the use
of random pattern generation methods [*] of testing requiring a large
number of random patterns to test cascaded AND networks.  BIST
designs are generally used and consist of two basic catagories: a
basic version and a simultaneous self-test (SST) version.  The basic
version will mimic LSSD testing configurations by loading the scan
string, firing the C clocks at the C clock inputs and then unloading
the scan string.  The basic version requires a minimal number of
logic cells but takes a relatively long time to achieve the high test
coverage required.  The SST version substitutes a self-test shift
register latch (SRL) for the normal SRL.  The result is an extremely
fast test.  However, an AND gate and an XOR gate were added to each
SRL which significantly increases the cell count.  In addition, the C
clock and data inputes to the SRLs are not fully tested.

      Basic LSSD testing typically involves the firing of a C clock
at the primary input.  It does not ensure that the C clocks at the
SRLs have been fired.  In many cases, the C clock is ANDed with a
number of other signals which must be in just the right state before
the C clock can latch the data at a particular SRL.  The set of
gating signals must be repeated again with a different data input
level before the SRL can be considered to be fully tested.  Since
test input data is of a relatively random nature, a large amount of
test sequen...