Browse Prior Art Database

Non-precise Interrupt Mechanism with Low Overhead for High Performance CPUs

IP.com Disclosure Number: IPCOM000110590D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR

Abstract

An architecture and hardware implementation is disclosed which provides a non-precise interrupt mechanism for high-performance processors. This interrupt mechanism has a very low overhead in terms of the amount of hardware required to implement as well as required additional levels of logic in the CPU critical paths.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Non-precise Interrupt Mechanism with Low Overhead for High Performance CPUs

       An architecture and hardware implementation is disclosed
which provides a non-precise interrupt mechanism for high-performance
processors.  This interrupt mechanism has a very low overhead in
terms of the amount of hardware required to implement as well as
required additional levels of logic in the CPU critical paths.

      Precise interrupts are very useful in general-purpose
processors.  A precise interrupt means that the interrupt-causing
instruction does not change the machine state or, if it changes the
machine state, there is a method for rolling the machine state back
to its value before the interrupt-causing instruction occurred.  As a
result, program execution may be resumed by re-executing the
interrupt-causing instruction after the interrupt has been serviced.
Precise interrupts are very expensive to implement in that they
require many logic gates and a substantial amount of silicon area.
Additionally, precise interrupts degrade the performance of the CPU
by preventing the interrupt-causing instruction from changing the
machine state when that instruction is in the critical path for the
CPU.  Additionally, precise interrupts are complicated and difficult
to implement, debug and tune for short cycle times.

      As depicted in the figure, the non-precise interrupt mechanism
includes an instruction and dispatch unit 10 which handles interrupts
and branches.  Functional units 12 receive instructions from the
dispatch unit and execute those instructions.  When a functional unit
has no instructions to execute, it notifies the dispatch unit by
raising the QUIESCENT line that is connected to the instruction
dispatch unit.  When a functional unit wishes to interrupt the
instruction e...