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Means for Generating a Pass A20 SignalfFrom a Single Register

IP.com Disclosure Number: IPCOM000110608D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Klim, PJ: AUTHOR

Abstract

Disclosed is a method by which a single register is used to generate a PASS A20 signal, when an I/O controller chip and a keyboard mouse controller chip, each of which has separate means for generating a PASS A20 signal, are combined into a single chip. This signal permits the use of address bit 20 when the processor operates in the virtual mode. Otherwise, the address space is limited to one megabyte during real mode operation.

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Means for Generating a Pass A20 SignalfFrom a Single Register

       Disclosed is a method by which a single register is used
to generate a PASS A20 signal, when an I/O controller chip and a
keyboard mouse controller chip, each of which has separate means for
generating a PASS A20 signal, are combined into a single chip.  This
signal permits the use of address bit 20 when the processor operates
in the virtual mode.  Otherwise, the address space is limited to one
megabyte during real mode operation.

      As shown in the figure, various blocks of logic 10 are used to
decode address information.  When the SYSTEM RESET signal is present,
during the power-on sequencing of the system, the PASS A20 register
bit is set or reset to zero, as required for the real mode of the
processor.  An I/O write to Port 92H is interpreted by the decode
logic of block 12 as a PASS A20 command, which is passed onward
through the steering logic of block 14 to clock data into the PASS
A20 register 16.  This register is then set in accordance with Data
Bit 1, so long as the SYSTEM RESET signal is not present, as
indicated by the -SYSTEM RESET input to AND circuit 18.

      Register 16 can also be reset from the keyboard mouse
controller (KMC) logic.  Whenever a Command D1 is issued to Port 64H
of keyboard mouse controller macro, the decode logic of block 20
provides an input to the decode logic of block 22.  If this command
is followed by an I/O write to Port 60H of the keyboard...