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Browse Prior Art Database

Module Interconnection using Hybrid Attachment

IP.com Disclosure Number: IPCOM000110611D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Foster, RA: AUTHOR [+3]

Abstract

Power and ground connections for modules are generally accomplished using pins on relatively gross grid dimensions (100 mils typically) and, since these pins are required to carry substantial current, they are composed of bulky metals. On the other hand, signal I/Os are generally more numerous and conduct low current. They can be implemented on a finer grid. In general, modules are built with either pins or solder bumps which sacrifices either real estate on the module or power distribution efficiency, respectively.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 81% of the total text.

Module Interconnection using Hybrid Attachment

       Power and ground connections for modules are generally
accomplished using pins on relatively gross grid dimensions (100 mils
typically) and, since these pins are required to carry substantial
current, they are composed of bulky metals.  On the other hand,
signal I/Os are generally more numerous and conduct low current.
They can be implemented on a finer grid.  In general, modules are
built with either pins or solder bumps which sacrifices either real
estate on the module or power distribution efficiency, respectively.

      The present invention suggests mixing pins and solder balls on
a single module.  This allows a larger number of I/Os for signal
while using pins to distribute power efficiently.

      Fig. 1 shows a side view of the invention.  A ceramic carrier 1
is used as an example with chips 2 C4 attached to the metallization
on the carrier.  Power is distributed to the chips via the pins 3 and
signal I/O is accomplished using solder balls 4.  The card 5 has
metallization 6 on fine grids to accept the bumps and PTHs 7 to
accept the pins.

      Fig. 2 shows a bottom view of the carrier.  The pattern clearly
shows the fine grid distribution for the signal I/Os, and the coarse
grid for the power pins.  Fig. 3 shows a side view of the module and
the card in mated relation.  The solder balls are connected first in
the preferred process and the power pins soldered subsequently, as
shown.

 ...