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Write Scheme for Multi-port CMOS Array

IP.com Disclosure Number: IPCOM000110623D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 29K

Publishing Venue

IBM

Related People

Behnen, E: AUTHOR [+4]

Abstract

Reading and writing an array within one cycle requires a cell, as shown in the figure, with separate bit lines for reading BLA, BLB and bit lines for writing DIC, DIT and also for each port a word line WLA, WLB, WLW. To minimize the cell area, a read operation is performed via the single bit lines and word lines. However, the write operation has to be carried out via the pair of bit lines carrying true and complement information. In the illustrated circuit, the write operation is started by the same clock trigger signal as the read operation; however, it is delayed and carried out during the read bit line restore phase.

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Write Scheme for Multi-port CMOS Array

       Reading and writing an array within one cycle requires a
cell, as shown in the figure, with separate bit lines for reading
BLA, BLB and bit lines for writing DIC, DIT and also for each port a
word line WLA, WLB, WLW.  To minimize the cell area, a read operation
is performed via the single bit lines and word lines.  However, the
write operation has to be carried out via the pair of bit lines
carrying true and complement information.  In the illustrated
circuit, the write operation is started by the same clock trigger
signal as the read operation; however, it is delayed and carried out
during the read bit line restore phase.

      By delaying the write operation with respect to the read
operation, the size of the cross-coupled devices can be reduced.
Additionally, switching data lines cannot couple noise into the
sensed bit lines because the read and write operations are staggered.