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Task Switching between Processes using the Sequencer

IP.com Disclosure Number: IPCOM000110626D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 104K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+4]

Abstract

One problem with a single-chip implementation of the IBM RISC System/ 6000* architecture is the amount of function needed to be handled on a single chip. One way to fix this problem is to use a general-purpose coprocessor that can handle all the tasks not implemented in dedicated hardware. This coprocessor, called the Sequencer, takes care of tasks that are not handled by the other execution units. Some of the tasks handled by the sequencer include all I/O processing, interrupt handling translation lookaside buffer (TLB) misses, real-time clock functions, and error handling. The problem with the sequencer handling all of the functions is that any or all of the tasks could need service at the same time. Naturally, some tasks take priority over other tasks and must be serviced quickly.

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Task Switching between Processes using the Sequencer

       One problem with a single-chip implementation of the IBM
RISC System/ 6000* architecture is the amount of function needed to
be handled on a single chip.  One way to fix this problem is to use
a general-purpose coprocessor that can handle all the tasks not
implemented in dedicated hardware.  This coprocessor, called the
Sequencer, takes care of tasks that are not handled by the other
execution units.  Some of the tasks handled by the sequencer include
all I/O processing, interrupt handling translation lookaside buffer
(TLB) misses, real-time clock functions, and error handling.  The
problem with the sequencer handling all of the functions is that any
or all of the tasks could need service at the same time.  Naturally,
some tasks take priority over other tasks and must be serviced
quickly.  Another problem that may occur is that while servicing one
task, it may become busy waiting for data from another unit.  This
waiting would cause the sequencer to waste processing cycles.  The
need to prioritize all of the tasks that need processing along with
being able to work on another task when one becomes busy is the goal
behind task switching.

      Built into the hardware of the I/O sequencer is the ability to
time slice  between three levels of processing routines.  These
routines are categorized as asynchronous processing, bus processing,
and instruction processing. Asynchronous routines have the highest
priority and must be serviced immediately.  Some asynchronous
routines include real-time clock servicing and system error
reporting.  The next level of routines falls under the category of
bus processing.  Bus processing routines include first and third
party DMA to the MICRO CHANNEL* bus.  The final level of routines are
instruction processing.  Instruction processing routines are used as
hardware assist for the fixed point unit.  Hardware assist routines
consist of move to special-purpose registers, TLB misses, and
programmed I/O (PIO).

      There are two instructions in the sequencer microcode
instruction set that provide for this task switching.  The names of
these instructions are Poll Service and Poll Service Halt.  Poll
service instructions are placed in the middle of an instruction
stream to allow for higher priority tasks to interrupt the program
flow.  For instance, in the middle of a progr...