Browse Prior Art Database

Enhanced Memory FIFO Buffer

IP.com Disclosure Number: IPCOM000110637D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Isaac, G: AUTHOR [+2]

Abstract

Disclosed is a buffering circuit for transferring data to and from an interleaved system memory, in which the circuit has buffering capacity equal to or greater than the number of words supported in burst reads and writes. With interleaving, the memory using this circuit can latch two words simultaneously, but the architecture of the system supports burst reads and writes of four words. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 76% of the total text.

Enhanced Memory FIFO Buffer

       Disclosed is a buffering circuit for transferring data to
and from an interleaved system memory, in which the circuit has
buffering capacity equal to or greater than the number of words
supported in burst reads and writes.  With interleaving, the memory
using this circuit can latch two words simultaneously, but the
architecture of the system supports burst reads and writes of four
words.

                            (Image Omitted)

      As shown in the figure, a local data bus 10 and a system data
bus 12 are connected to four latches 14, each of which is capable of
storing a single word of data.  A first data bank is connected to a
pair of latches 16, and a second data bank is connected to another
pair of latches 18.  Each of these individual latches 16 and 18 is
similarly capable of storing a single word of data.  A multiplexer 20
steers signals among the various latches.

      Using one of the data buses 10 or 12 in writing to memory, a
device can latch four words into memory in a FIFO (First-In,
First-Out) order, in four consecutive clock pulses, assuming one word
per clock pulse.  Once the fourth word is latched, the device can
continue with another operation or relinquish the bus.  Meanwhile,
the data is written to memory.  After a four-word burst read from an
I/O device, a four-word burst write to memory occurs.  Since the
burst write appears complete to the DMA (Direct Memory Access)...