Browse Prior Art Database

Programmable Identification Scheme

IP.com Disclosure Number: IPCOM000110640D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Clarke, GL: AUTHOR [+4]

Abstract

A programmable identification scheme provides the identification of different systems, such as, various IBM PS/2* personal computer systems. This scheme or method reads identification (ID) bytes via programmable option select (POS) addresses to permit setting up I/O logic chip to be used in several generations and types of PS/2 systems.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Identification Scheme

       A programmable identification scheme provides the
identification of different systems, such as, various IBM PS/2*
personal computer systems.  This scheme or method reads
identification (ID) bytes via programmable option select (POS)
addresses to permit setting up I/O logic chip to be used in several
generations and types of PS/2 systems.

      Assigned bits in planar POS 94H each enable or disable a group
of addresses 100H through 107H that permit to setting up various
devices internal or external to the planar I/O logic chip.  Upon
Power on Reset (POR) all bits come up as logic ones.  Thus, the
planar I/O logic chip's set-up addresses are disabled.  To access ID
ports 100 and 101, bit 7 in port 94 must be set to zero to
enable the set-up addresses of level A, with each of the remaining
bits being at one.

      The planar I/O logic chip contains seven POS IDs for system
identification which may be read via the data bus during I/O read
operations to ports 100H and 101H when the planar I/O logic chip is
in set-up level A.  An I/O write operation to either port is ignored.
Each pair of ID bytes to be read is determined by the value of I/O
pins +ID S0 and +ID S1, and the input pin +ID S2.  These pins are
tied to ground or supply voltage VDD via resistors R1, R2 and R3 as
indicated in the figure to assign the corresponding ID for each
system.  The values of +ID S0, +ID S1 and +ID S2 for any given ID
are indicated in Table 1.  If +ID S0, +ID S1 and +ID S2 are all
pulled high, bidirectional pins +ID S0 and +ID S1 become outputs and
read strobes are passed via both pins which permits additional IDs
external to the planar I/O logic chip.  Then +ID S0 is used to pass
the read strobe for port 100H and +ID S1 is used to pass the read
strobe for port 101H.

      +ID S2    +ID S1    +ID S0    Port 100H ID   Port 101H ID
        0         0         0  ...