Browse Prior Art Database

Anticipatory Generation of Addresses for Microprocessors

IP.com Disclosure Number: IPCOM000110642D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 156K

Publishing Venue

IBM

Related People

Galella, JW: AUTHOR [+3]

Abstract

Described is an architectural logic implementation that provides a method of generating anticipatory addresses in microprocessor operation so as to improve memory access time. Utilized is an anticipatory page mode simulated pipelining method.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Anticipatory Generation of Addresses for Microprocessors

       Described is an architectural logic implementation that
provides a method of generating anticipatory addresses in
microprocessor operation so as to improve memory access time.
Utilized is an anticipatory page mode simulated pipelining method.

      Microprocessors, such as the Intel 80486*, typically interface
to a dynamic random access memory (DRAM) through: address lines, data
lines, a row address strobe (RAS), a column address strobe (CAS), and
write enable (WE) lines.  Error correction code (ECC) can be employed
in the DRAM subsystem to facilitate the detection and correction of a
single-bit error in a 32-bit word and to detect, but not correct, a
two-bit error in a 32-bit word.  Due to the extensive checking
provided by the ECC memory, there is often a performance penalty for
memory accesses when compared to the typical parity memory
implementation.  The need to lessen the effects on performance when
using ECC memory is one of the aspects discussed in the following
examples.  The concepts discussed are also applicable to parity
memory designs.

      The 80486 microprocessor is designed to provide a burst mode
function for data transfers and require more than a single data
cycle.  Fig. 1 shows a timing chart of the 80486 burst mode cycle.
When in the burst mode cycle, valid data can be loaded to the
microprocessor at every subsequent clock transition until the data
transfer is complete.  The burst mode is used to transfer 16-bytes of
data to the microprocessor.  If a 32-bit data path is used from the
DRAM, only 4 cycles are required to transfer 16-bytes.  The speed of
the DRAM subsystem is the main limitation for valid data to be
available to the microprocessor.

      Fig. 2 shows a table of the burst mode address sequence.  The
order of addresses A2 and A3 out of the microprocessor is determined
by the first transfer in the cycle.  Addresses A2 and A3 are valid
after the start of each microprocessor T1 or T2 time, as shown in
Fig. 1, and are valid until the -BURST READY signal is sampled at the
start of the next microprocessor T state.  The microprocessor wait
states, 40 ns in this example, are added to the burst mode cycle by
not driving the -BURST READY signal active at the start of the next T
state.  Typically, the DRAM subsystem cannot operate without adding
wait states for each data transfer.

      Fig. 3 shows the timing chart for a DRAM page mode operation
which can provide data at a faster transfer rate than non-paged
operation.  The DRAM used for illustrating this example can provide
data in 80 ns when in non-paged mode and 40 ns when in paged mode.

      Fig. 4 shows the timing chart interface for the typical page
mode DRAM.  This page mode implementation for the 80486 requires a
DRAM subsystem to add...