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L1/L2 Replacement Strategy

IP.com Disclosure Number: IPCOM000110643D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Getzlaff, KJ: AUTHOR [+3]

Abstract

This article describes an L1/L2 replacement strategy in a closely coupled shared memory system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

L1/L2 Replacement Strategy

       This article describes an L1/L2 replacement strategy in a
closely coupled shared memory system.

      To keep the memory bus from becoming the performance
bottleneck, the processors of the closely coupled shared memory
system must use this bus only very rarely.  This is accomplished by a
store-in L2 concept which ensures that the memory bus is needed only
when a dirty line is replaced in the L2 cache or a new line is
loaded in response to an L2 cache miss.  However, when another
processor accesses the same cache line as stored in the L2 cache, a
protocol for maintaining data integrity is to be observed.

      In the described system, a multiple copy bit is set whenever
there is more than one copy in the system.  Before a processor can
store into a line thus flagged, it has to invalidate all other copies
in the system.  This involves broadcasting the memory activities for
all processors.  Such broadcasting consists of watching the various
processors fetching lines from the main memory and forcing the
multiple copy bit ON, if required.  Broadcasting also consists of
invalidating multiple copies when a processor stores into a line.
Compared to state of the art machines, interfering with the
processors for performing such broadcasting activities is eliminated
in the described system, as all lines are in the L2 cache.  These
lines are up to date, as the L1 cache works on the store-through
concept.  As a result, the L2 can assign a line to another processor
if the line has been changed and another processor requires access
thereto.  However, most broadcasting is just watching the bus and
comparing fetch addresses of other processor...