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Output Buffer Circuit of Low Switching Noise and Low Power Dissipation

IP.com Disclosure Number: IPCOM000110652D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Hino, A: AUTHOR [+2]

Abstract

Disclosed is a circuit to realize low switching noise and low power dissipation and high source/sink current at one time. The circuit is mainly used for an output buffer of LSI.

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This is the abbreviated version, containing approximately 75% of the total text.

Output Buffer Circuit of Low Switching Noise and Low Power Dissipation

       Disclosed is a circuit to realize low switching noise and
low power dissipation and high source/sink current at one time.  The
circuit is mainly used for an output buffer of LSI.

      Output buffer circuits have transistors of large current
driving capability at their final stage.  As their driving capability
increases, dV/dt noise and transient rush current during switching
generally increase as well.  By dividing transistors of the final
stage into two or more parallel transistors and controlling added
parallel transistors by a special switching circuit which is composed
of pass-gates (transfer gate) and pull up/down transistors, dV/dt
noise and rush current can be reduced without changing source/sink
current specification.

      The figure is a sample circuit of a tri-state CMOS buffer which
adopts this technique.  In this example, two pairs of P/N channel
FETs are used as final stage transistors, but this selection of
transistor type has no relation to the essential concept of this
technique, and those transistors are easily replaced by ones of other
types.  In addition, the second pair of P/N FETs can be selectively
used by control signal E as a natural extension of the technique,
that is, it can be consecutively off during operation in case lower
driving capability is required by the buffer.  The truth table is
shown as Table 1.

      The timing sequence of T1p/n,...