Browse Prior Art Database

Improved Real Time Wrap Back Driver Checking

IP.com Disclosure Number: IPCOM000110656D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 143K

Publishing Venue

IBM

Related People

Drehmel, RA: AUTHOR [+2]

Abstract

This article describes a means for checking proper output driver operation. Correct function of the driver or I/O driver is determined by using a receiver and comparing the expected to actual value driven. This technique uses no additional pins. Checking is performed after each transition should occur using either a fixed or programmable delay. The result is a real-time check for a stuck at 0 or 1 on the driver output. As such, driver failures or shorted nets can be accurately detected.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Improved Real Time Wrap Back Driver Checking

       This article describes a means for checking proper output
driver operation.  Correct function of the driver or I/O driver is
determined by using a receiver and comparing the expected to actual
value driven.  This technique uses no additional pins.  Checking is
performed after each transition should occur using either a fixed or
programmable delay.  The result is a real-time check for a stuck at 0
or 1 on the driver output.  As such, driver failures or shorted nets
can be accurately detected.

      A technique for error detection on drivers or I/O drivers is
described.  Specifically, certain drivers cannot be checked at the
receiving components such as the control lines driven to the memory
components in a memory sub-system.  By performing a real-time check
of the driver, proper fault isolation can take place.

      In order to check these control lines, a form of wrap-back
checking has been used.  This requires that the output driver be
modified to be a driver/receiver, or that a separate receiver be
added.  The purpose of the receiver is to echo back a copy of the
output to be used as a compare against an internal expect value.
This technique does not use duplicate drivers or any extra pins to
perform the checking.  The receiver value is compared against the
expect value a predetermined amount of time after the driver is
enabled with new data.  This delay is necessary in cases where the
switching time of the net may be longer than a clock cycle.  The
amount of delay can be programmable (by cycle increments) in order to
adjust the value to ensure successful implementation.  A register
value can be used to control this delay value (see the figure).

      In the figure, all of the logical blocks without an '*'
represent a driver implementation without wrap-back checking.  The
blocks with the '*'s are the additional logic used to perform the
checking as described within this invention.  DRAMs are typically
enabled by bringing the control inputs from high to low.  This is
accomplished by enabling SETLO active for 1 cycle.  The
implementation shown is for a non-clock gated latch with gating on
the data such that the latch value is maintained while SETLO and
SETHI are both low.  SETHI going active for 1 cycle causes the output
of the latch to go high and stay high until SETLO is active.  The
driver and preceding logic are designed such that only SETLO or SETHI
will be enabled at any one time.

      The output labeled STUCK DRIVER ERROR OUTPUT will be active if
a mismatch occurs between the latch driving data to the driver and
the value determined by the receiver.  With multiple drivers on a
logic compo...