Browse Prior Art Database

Early Start Bit Detector

IP.com Disclosure Number: IPCOM000110661D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Carey, JE: AUTHOR [+3]

Abstract

A circuit is disclosed which senses the beginning of the start bit of an asynchronous communication protocol. An output is generated in a time short with respect to the duration of the start bit. When sent to other user-generated circuits, this early start bit detect signal allows real-time manipulation of a data frame.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Early Start Bit Detector

       A circuit is disclosed which senses the beginning of the
start bit of an asynchronous communication protocol.  An output is
generated in a time short with respect to the duration of the start
bit.  When sent to other user-generated circuits, this early start
bit detect signal allows real-time manipulation of a data frame.

      Referring to the figure, the start bit detection sequence is
initiated by a level transition at the DATA MONITOR input 3.  The
START BIT DETECTION circuits 9 use FAST CLOCK IN 8 as a sampling
timer.  If the signal at DATA MONITOR 3 remains valid for some
arbitrary number of cycles of FAST CLOCK IN 8, START BIT DETECTION
circuits 9 will generate a LATCHED START DETECT output 5.  The time
during which FAST CLOCK IN 8 samples DATA MONITOR 3 should be kept
short with respect to the bit time of the data transmission.  LATCHED
START DETECT output 5 can now enable other circuits external to the
present discussion to act upon the data frame in real time.

      Further timing is necessary to reset the START BIT DETECTION
circuits 9 at the end of the data frame.  This is accomplished by the
BIT COUNTER/LEVEL DETECTOR circuits 10.  In addition to counting
bits, this circuit is used to add robustness to the overall design by
retesting the validity of the LATCHED START DETECT output 5.

      The BIT COUNTER/LEVEL DETECTOR 10 is enabled by the LATCHED
START DETECT output 5.  At approximately the midpoint...