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Oscillator Fail Detection Circuit

IP.com Disclosure Number: IPCOM000110662D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Gillingham, RD: AUTHOR [+2]

Abstract

A circuit is described that will detect when an oscillator has stopped oscillating. The method utilizes only digital circuitry and is insensitive to the frequency of the oscillator.

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Oscillator Fail Detection Circuit

       A circuit is described that will detect when an
oscillator has stopped oscillating.  The method utilizes only digital
circuitry and is insensitive to the frequency of the oscillator.

      Fig. 1 shows the circuit to be described.  An oscillator
signal, OSC, is sampled by the positive edge of a clock signal, CLK.
Another input, POR, resets the logical gates, 1-7, and 11, at
power-on.  The output, +Fail, indicates when the OSC signal has
stopped switching (stuck low or high).

      Gates 1 to 7 and 11 are D Flip Flops with data input D,
clock C, Reset R, and outputs Q and N (inverted Q).  Each time the
CLK signal goes positive (assuming +edge-sensitive latches), the DFFs
gate the signal at input D to the output at Q.

      Fig. 2 shows a typical output sequence where the oscillator
(OSC) quits oscillating.  In this case, the oscillator stays low (the
dotted pulses show where the oscillator should have pulsed if it had
not failed).

      DFFs 1 to 7 form a shift-register that shifts the data by 7
pulses.  Seven CLK pulses after the OSC input stays low, all of the
DFFs have a down-level output (signals 1P to 7P).  This causes NOR-8
to become active, activating OR-10.  On the next negative edge of the
CLK, the inverter 12 clocks the OR-10 output to the +Fail line.

      If the OSC input had stuck high, all of the DFF's complementary
outputs, 1N to 7N, would have gone high, activating NOR-9.  This
wo...