Browse Prior Art Database

Active Push Pull Load for High Speed Bipolar Circuits

IP.com Disclosure Number: IPCOM000110668D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Shin, HJ: AUTHOR

Abstract

A new active push-pull load or current sink for high-speed low-power bipolar/BiCMOS digital logic circuits is disclosed as shown in the figure. The circuit provides a constant steady-state sink current but actively modulates the sink current for push-pull operation during signal transitions. This new load circuit can be applied to heavily capacitive nodes as a high-speed pull-down element with minimum power. It allows the emitter-dotting which is very valuable for implementing complex logic functions without adding gates and power consumption, in contrast to the prior-art active pull-down ECL/NTL circuits where the emitter-dotting cannot be applied.

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Active Push Pull Load for High Speed Bipolar Circuits

       A new active push-pull load or current sink for
high-speed low-power bipolar/BiCMOS digital logic circuits is
disclosed as shown in the figure.  The circuit provides a constant
steady-state sink current but actively modulates the sink current for
push-pull operation during signal transitions.  This new load circuit
can be applied to heavily capacitive nodes as a high-speed pull-down
element with minimum power.  It allows the emitter-dotting which is
very valuable for implementing complex logic functions without adding
gates and power consumption, in contrast to the prior-art active
pull-down ECL/NTL circuits where the emitter-dotting cannot be
applied.

      The transistor Q1 in the figure is used for pull-down current
sink, Q2 for biasing, Q3 for inverting, R1 for
level-shifting/coupling, R2 for current and gain setting, and R3 for
discharging the bases of Q1 and Q2.  Note that R1 can be replaced by
a level-shifting diode.  Optionally, capacitors C1, C2, and diode D2
can be added to increase coupling, tune push-pull action, and clamp Z
to prevent saturation of Q3, respectively.  The terminal T of this
push-pull load is to be connected to the emitter or dotted-emitters
of emitter followers, as shown.

      The new circuit sets the steady-state bias and pull-down
currents constant through self-regulation and current-mirroring.  In
steady states, because the current in R2 is (VCC - VEE - VBE(Q2) -
VS(R1)) / R2 and the current in R1-R3 branch is VBE(Q2) / R3, the
bias current for Q2-Q3 is determined as ((VCC - VEE - VBE(Q2) -
VS(R1)) / R2 - VBE(Q2) / R3) where VS(R1) is the level-shift voltage
across R1, i.e., VBE(Q2) * R1 / R3.  This bias current for Q2-Q3 is
mirrored to Q1 as the pull-down current with a multiplication factor
equal to ar...