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Browse Prior Art Database

Method of Increasing Capacitance Area using RIE Selectivity

IP.com Disclosure Number: IPCOM000110675D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+3]

Abstract

Disclosed is a new method of increasing the surface area of a capacitor used in DRAM. It utilizes the difference in Reactive Ion Etch (RIE) rate of two materials to enhance the topological features of one plate of the capacitor, resulting in an area increase.

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This is the abbreviated version, containing approximately 52% of the total text.

Method of Increasing Capacitance Area using RIE Selectivity

       Disclosed is a new method of increasing the surface area
of a capacitor used in DRAM. It utilizes the difference in Reactive
Ion Etch (RIE) rate of two materials to enhance the topological
features of one plate of the capacitor, resulting in an area
increase.

      The concept of the new method is shown in Figs. 1 and 2.  As
shown in Fig. 1, assume that we have a few tens of nanometers thick
silicon dioxide layer.  It has hemispherical bumps on its surface and
the bumps are a few tens of nanometers in diameter, whose profile is
shown as the solid line.  A silicon nitride layer is placed between
the silicon oxide and silicon layer.  First, we etch the silicon
dioxide and transfer its profile to the silicon nitride.  Any etching
gas can be used as long as it has a good directionality and a
reasonable etch rate.  The profile is shown as the second curve from
the top in Fig. 1.  After transferring the profile to the nitride
layer, we will change to an etching gas which etches silicon faster
than the silicon nitride.  Assume the etch rate ratio, or selectivity
is about 10.  A good candidate is a mixture of CF4 + O2 at a
few tens of millitorrs.  As shown in the successive curves, the
profile will change from hemispherical shapes to spheroidal shapes as
the silicon nitride is completely etched away because the difference
in the etch rate will make those area cleared of silicon nitride
sooner etch faster than the rest.  Fig. 2 illustrates the etching
step three-dimensionally and graphically shows the increase in the
surface area.

      An application of the above idea to DRAM is shown in Fig. 3 and
is also explained below:
(A) The transfer device is formed following the standard MOS
processes.  This includes formation of the wordline as well as
bitlines.  A contact opening is made to the drain of the transfer
device.  Pol...