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Technique to Manufacture High Performance, Shallow Junction CMOS Devices

IP.com Disclosure Number: IPCOM000110682D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 98K

Publishing Venue

IBM

Related People

Agnello, PD: AUTHOR [+2]

Abstract

A CMOS process is described to provide n-channel and p-channel devices with shallow junctions for high performance operation. A technique is also presented for contacting these shallow junctions.

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Technique to Manufacture High Performance, Shallow Junction CMOS Devices

       A CMOS process is described to provide n-channel and
p-channel devices with shallow junctions for high performance
operation.  A technique is also presented for contacting these
shallow junctions.

      Shallow junctions are required as device dimensions are scaled
down to obtain high density and high performance ICs.  This is since
shallow junctions provide reduced device capacitance, reduced device
resistance and well-controlled device characteristics, such as Vt
roll-off.  Simultaneously, manufacturing shallow junctions for the
NMOS and PMOS devices in a CMOS technology, as well as contacting
these junctions, has been a problem due to the constraint in reducing
the thermal cycles used after forming these shallow junctions.  In
this article, a  technique to integrate two different methods to form
shallow junctions for the NMOS and PMOS devices while providing a
high performance CMOS technology is presented.  This technique also
solves the problem of contacting these shallow junctions while
limiting the thermal cycles used after their formation.

      For the NMOS devices the shallow junctions are formed by using
low energy, low dose As or Sb ion implants.  For PMOS devices the
shallow junctions are formed by out-diffusing Boron from Boron doped
oxide, e.g., BSG.  The process of forming these junctions and the
method to contact them is described in the following ten steps:
1.  After gate definition (n+ poly for NMOS and p+ poly for PMOS) in
a standard CMOS fabrication sequence, 10 nm poly sidewa...