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AC Self Test Across Asynchronous Logic Partitions

IP.com Disclosure Number: IPCOM000110693D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 56K

Publishing Venue

IBM

Related People

Dillinger, JR: AUTHOR [+3]

Abstract

In systems in which a Common On-Chip Processor (COP) controls the logic self-test functions, each time a logic self-test is executed the COP performs the following sequence of operations: (1) The COP loads pseudo-random patterns into the Shift Register Latches by activating the Shift Register Latches' SCAN GATE control signal and sequencing the master and slave clocks; (2) The SCAN GATE signal is deactivated and slave clock is cycled once followed by a master clock cycle. This allows the pseudo-random patterns to propagate out of the slave latches through logic circuits and to be sampled by a master latch.

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AC Self Test Across Asynchronous Logic Partitions

      In systems in which a Common On-Chip Processor (COP) controls
the logic self-test functions, each time a logic self-test is
executed the COP performs the following sequence of operations:
(1) The COP loads pseudo-random patterns into the Shift Register
Latches by activating the Shift Register Latches' SCAN GATE control
signal and sequencing the master and slave clocks;
(2) The SCAN GATE signal is deactivated and slave clock is cycled
once followed by a master clock cycle.  This allows the pseudo-random
patterns to propagate out of the slave latches through logic circuits
and to be sampled by a master latch.  Since the pattern must
propagate through the logic in one cycle, AC logic testing is
provided;
(3) The shift register latch data is scanned out into a
Multiple-Input Signature-Compression Register (MISR);
(4) Steps 1-3 are repeated for a fixed number of cycles and the
signature is then read out and verified.

      A problem occurs with this self-test methodology when a chip
contains multiple logic partitions which operate on separate
asynchronous clocks.  Patterns which cross an asynchronous boundary
may be in an indeterminate state with respect to the sample clock of
the receiving partition.  This indeterminate data contaminates the
signature.

      A solution to this problem is provided by adding a clock
controller to the master and slave clocks of each logic partition
which is not in sync with...