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Boundary Scan Compatible Pullup Receiver Allowing Product IDD Testing

IP.com Disclosure Number: IPCOM000110712D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 35K

Publishing Venue

IBM

Related People

Stout, DW: AUTHOR

Abstract

An active pullup circuit is described for logic level inputs to an on-chip CMOS receiver. All active pullup circuits on a chip are disabled during Idd defect testing by a single Receiver Inhibit (RI) line so that all intentional dc paths are inhibited and testing is compatible with boundary scan design principles.

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This is the abbreviated version, containing approximately 100% of the total text.

Boundary Scan Compatible Pullup Receiver Allowing Product IDD Testing

      An active pullup circuit is described for logic level inputs to
an on-chip CMOS receiver.  All active pullup circuits on a chip are
disabled during Idd defect testing by a single Receiver Inhibit (RI)
line so that all intentional dc paths are inhibited and testing is
compatible with boundary scan design principles.

      A schematic of the active pullup circuit is shown in the
figure.  In the Idd test mode, the RECEIVER INPUT and the RI line are
held at logic level 0 (down level) so that T3 is off, T2 is on,
T1 is off and RECEIVER TRUE OUTPUT is at logic level 1 (up level).
Since T1 is off, all intentional dc paths through the circuit are
inhibited during the Idd test mode.

      In the normal operating mode, RI is at logic level 1, T3 is on,
T2 is off, T1 acts as a pullup resistance and RECEIVER TRUE OUTPUT
follows RECEIVER INPUT.  Since the RI line is required for boundary
scan design, no new control signals are required to implement the
active pullup function.

      Disclosed anonymously.