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Technique for Improving Logic Simulation Effectiveness through the Use Of Randomly Altered Block Delays

IP.com Disclosure Number: IPCOM000110745D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Cash, RC: AUTHOR

Abstract

This article describes an algorithm for randomly dithering the predicted delays of logic blocks about their nominal values for the purpose of uncovering race conditions during simulation. Thus, a designer has a better chance of detecting timing errors which might result because the circuit delays in the actual hardware are slightly different than the delays predicted by the design automation tools.

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Technique for Improving Logic Simulation Effectiveness through the Use Of Randomly Altered Block Delays

       This article describes an algorithm for randomly
dithering the predicted delays of logic blocks about their nominal
values for the purpose of uncovering race conditions during
simulation.  Thus, a designer has a better chance of detecting timing
errors which might result because the circuit delays in the actual
hardware are slightly different than the delays predicted by the
design automation tools.

      An important part of designing a new logic component is to
detect race conditions produced by unequal delays through different
parts of the logic.  The problem is especially prevalent in designs
which receive signals which are not synchronized to the component's
system clock.  Ideally, all race-sensitive paths should be thoroughly
analyzed by a designer to ensure proper operation across all
operating conditions.  Unfortunately, for most designs of moderate
complexity it becomes extremely difficult to reliably identify all
possible races.  In this case it is common practice to use a logic
simulator to help identify those paths.

      Event-driven simulators, such as IBM's AUSSIM simulator, rely
on accurate descriptions of the target technology's gate delays.  The
more accurate the delays, the more closely the results predicted by
the simulator will match the actual circuit.  AUSSIM can use either
its fixed intrinsic gate delays and loading adder or can read the
more accurate delays generated by IBM's ETE (Early Timing Estimator).
In either case, the predicted delays remain the same for any given
circuit for all simulations.  Therefore, a marginal timing path may
pass all available simulations and thus be hidden from the attention
of the designers.  Paths which had marginal timing using estimated
delays may turn out to be true race conditions in the final product.

      One technique that has been used to check for hidden race
conditions is guard banding. Guard banding adds a...