Browse Prior Art Database

Packet-Processing First-In, First-Out

IP.com Disclosure Number: IPCOM000110764D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Dotson, MW: AUTHOR [+5]

Abstract

Disclosed is a hardware First-In, First-Out (FIFO) with new features to assist the passing of message packets among nodes of a parallel system. In most message-passing systems, a packet is sent from a first node to a message Send FIFO on the local adapter which connects the first node to a network. In turn, the first local adapter sends the packet from the Send FIFO through the network to a second node through its associated second local adapter. After traversing the network, the packet is received and placed in a Receive FIFO, which in turn transfers the packet to the second node. The Send FIFO storing the packet to be sent to the network is different than the Receive FIFO receiving the packet from the network. However, the same disclosed features can be used for both of the packet-passing FIFOs.

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This is the abbreviated version, containing approximately 52% of the total text.

Packet-Processing First-In, First-Out

      Disclosed is a hardware First-In, First-Out (FIFO) with new
features to assist the passing of message packets among nodes of a
parallel system.  In most message-passing systems, a packet is sent
from a first node to a message Send FIFO on the local adapter which
connects the first node to a network.  In turn, the first local
adapter sends the packet from the Send FIFO through the network to a
second node through its associated second local adapter.  After
traversing the network, the packet is received and placed in a
Receive FIFO, which in turn transfers the packet to the second node.
The Send FIFO storing the packet to be sent to the network is
different than the Receive FIFO receiving the packet from the
network.  However, the same disclosed features can be used for both
of the packet-passing FIFOs.

      The disclosed packet-processing FIFOs work together to
guarantee accurate delivery of the packet once it is stored to the
Send FIFO.  If the FIFOs detect an error in the transmission of the
packet over the network, they cancel the erroneous transmission, and
have the ability to cycle back and to resend the erroneous packet
from the beginning without interrupting the first, second or any
node.  The FIFOs are completely self-sufficient, and off-load the
nodes while providing instantaneous recovery and fault tolerance.

      The read and write functions of each FIFO are each controlled
by a pointer and a counter, as shown in the figure in relation to the
Send FIFO.  Initially, a reset signal resets all pointers...