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Asymmetric Transition Dual-Rail Signalling

IP.com Disclosure Number: IPCOM000110777D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR

Abstract

Disclosed is a style (form) of self-timed logic whose correct circuit behavior is dependent neither on component speeds nor communication wire delays. It is called Asymmetric Transition Dual-Rail (ATDR) signaling, and differs from traditional dual-rail signaling by not requiring spacer tokens between data tokens. ATDR can increase throughput by as much as 100% in pipelined logic, and it is applicable to both pipelined and feedback logic structures. Transistor and gate level logic implementations are provided for comparison.

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Asymmetric Transition Dual-Rail Signalling

      Disclosed is a style (form) of self-timed logic whose correct
circuit behavior is dependent neither on component speeds nor
communication wire delays.  It is called Asymmetric Transition
Dual-Rail (ATDR) signaling, and differs from traditional dual-rail
signaling by not requiring spacer tokens between data tokens.  ATDR
can increase throughput by as much as 100% in pipelined logic, and it
is applicable to both pipelined and feedback logic structures.
Transistor and gate level logic implementations are provided for
comparison.

      An earlier publication [1]  provides an extensive discussion of
self-timed logic, and its advantages in comparison to globally
clocked or synchronous logic.  A main advantage is that individual
logic blocks can signal to other partitions as soon as their
functions are completed, rather than having to wait for a worst-case
delay within a global network of associated units.  In synchronous
designs, the worst-case delay is factored into the clock cycle time.

      Dual-rail signalling is a widely used style of self-timed
logic.  In one such style, called 4-phase dual rail, signals are used
to represent three discrete logic levels or values: 0, 1 and invalid.
Each logic variable x is encoded using two wires (or rails) to
represent its instantaneous true and complement states.  Ordinarily,
signals on the two wires representing a variable are required to
return to the invalid state after the data value of the variable has
been taken (accepted by another circuit).  In essence, the return to
the invalid state serves as a spacer token between successive data
token values, so that equal successive values are accurately
distinguishable from each other.

Figure 1

Single-Rail       0     0      1     0     0      1     1     1

4-Phase Dual-Rail 01 00 01 00  10 00 01 00 01 00  10 00 10 00 10

Transition Sig.   00    01     11    10    11     01    11    01

ATDR              00    01     11    01    00     10    11    10

      Several methods of designing self-timed logic are presented in
[1,2,3,4].  In these, the functional delay through a logic block for
a spacer token is approximately the same as that for a data token.

Other dual-rail designs [5] use a control signal to reset or
precharge individual gates in the logic block between acceptances of
successively presented input data tokens.  The precharge may have
less functional delay per block than the spacer token methods.

      An alternative is to use a transition signalling technique in
which only one wire in any two-rail pair changes state between
consecutive data token inputs.  Perhaps the most obvious way to
achieve this is to interpret a transition on a pre-arranged one of
the wires, for instance on the wire manifesting the true value, as
indicating the beginning of a new datum value for the...