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RISC Central Processor Unit Pipeline Modeling Interconnection Language

IP.com Disclosure Number: IPCOM000110790D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 4 page(s) / 136K

Publishing Venue

IBM

Related People

Gariazzo, RE: AUTHOR

Abstract

The RISC Central Processor Unit Pipeline Modelling Interconnection Language is an approach to simplify the definition of a RISC pipeline configuration through graphical symbols. This language is used in the "RISC Superscalar Parametric Processor Modeller" used to create the TIMER for the Graphics Floating Point Engine.

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This is the abbreviated version, containing approximately 51% of the total text.

RISC Central Processor Unit Pipeline Modeling Interconnection Language

      The RISC Central Processor Unit Pipeline Modelling
Interconnection Language is an approach to simplify the definition of
a RISC pipeline configuration through graphical symbols.  This
language is used in the "RISC Superscalar Parametric Processor
Modeller" used to create the TIMER for the Graphics Floating Point
Engine.

      The Graphics Floating Point Engine (GFPE), is a Superscalar
Micro Processor based on the RISC System/6000 POWER PC architecture,
used in Graphics and Multimedia applications.  It is a single chip
implementation that contains an Instruction cache, a Data cache, a
Branch Processor, a Superscalar Unit, two Fixed Point Units, two Load
Store Units, and three Floating Point Units.

Problem Description - One of the most cumbersome aspects of creating
a mode l of a CPU is the declaration of the connections of the
internal stages that are part of the pipeline:  execution or cache or
memory stages.  The problem arises due to the complexity of a RISC
pipeline interconnection and to the many forms the connections may
take.  A second problem is the difficulty in visualizing the pipeline
connectivity flow once the model has been written.

Solution Presented - The solution is an interconnection language
oriented to RISC pipeline implementations, which is based on the
common factors of these connections.  This language contains all the
information of the protocol between the connected stages, and is
graphical in its context to better visualize the flow of instructions
and controls within the pipeline.

Advantages - The goal for this language is to be simple and symbolic,
but flexible enough to define most of the aspects of the connections.

Description - The RISC Central Processor Unit Pipeline Modelling
Interconnection Language has two basic concepts:  flow and direction.
"FLOW" can be address, control, data or instructions.  "DIRECTION"
defines the transfer itself as well as the distribution of the
information being transferred.  The language also allows parameters
defining how the information will be handled by the units involved in
the transfer.

      The language has the capability to handle execution stages as
well as storage (or cache) stages.  Its structure is shown in Fig. 1.

      There are two areas in the structure of the language:  a MASTER
and a SLAVE area.  The Master is those stages that can initiate
requests, either for data or instructions.  These stages can only be
EXECUTION UNITS (either requesting data or instructions from a
storage unit).  The Slave is those stages that make information
available, either data or instructions, to the master stages.  These
stages may be EXECUTION UNITS or STORAGE/MEMORY UNITS.

      The direction of the transfer is controlled by the characters
combination of '-' (dash) and '>' (greater than) or '<<' (less than).

The character set defined in this language is:

     SET "-...