Browse Prior Art Database

Paralleling Multiple Asynchronous Networks for Improved Bandwidth

IP.com Disclosure Number: IPCOM000110816D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 96K

Publishing Venue

IBM

Related People

Deshpande, SR: AUTHOR [+4]

Abstract

Disclosed is a method for using multiple asynchronous networks in parallel to provide increased bandwidth and wider data paths through multi-stage networks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Paralleling Multiple Asynchronous Networks for Improved Bandwidth

      Disclosed is a method for using multiple asynchronous networks
in parallel to provide increased bandwidth and wider data paths
through multi-stage networks.

      One type of multi-stage network that provides many
state-of-the-art features is the asynchronous circuit-switched
network.  The network establishes a direct connection path through
the network from sender to receiver, and data is not stored or held
in the network itself.  Message accuracy is checked at the receiver,
and rejected all the way back to the sender if an error is detected.
The sender has the capability to retry the message.  However,
asynchronous networks are hard to parallel because they share no
common clocks.  This disclosure details one solution using a
synchronization method based on the reject and retry function.

      The Figure shows a typical 8-input port and 8-output port
asynchronous switch chip implementing the reject and retry function.
The basic chip provides for byte-wide data transfers through a
multi-stage network comprised of multiple cascaded copies of the
switch chip.  Paralleling two-byte-wide networks would provide a
16-bit-wide data path through the network and double the bandwidth of
the network.  Likewise, paralleling more than 2 switch chips would
continue to increase the data width and bandwidth.

      The Figure illustrates the disclosed synchronization method for
paralleling three 8x8 switch chips (12A, 12B and 12C).  The three
asynchronous switch chips are kept aligned by using external OR and
AND gates, as typified by gates 20 and 22.  Each switch port has 2
feedback control lines called REJECT and ACCEPT.  REJECT is activated
if any commanded connection in the switch or network cannot be made
as commanded, or if the message sent through the switch network is
not received properly at the receiving node of the network.  ACCEPT
is activated if the message sent through the switch network is
received properly at the receiving node of the network.

      All 3 chips - 12A, 12B and 12C - are commanded simulta...