Browse Prior Art Database

Bus-Master Service Adapter for High-Availability Computers

IP.com Disclosure Number: IPCOM000110833D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Goal, PM: AUTHOR [+2]

Abstract

Disclosed is a bus-master service adapter that provides access to the I/O subsystem of a failed machine by another machine which is simultaneously the source of redundancy used to attain high availability. This is an advanced version of a previously proposed service adapter. In addition to the capabilities of the service adapter - e.g., power control and monitoring facilities - the advanced service adapter provides access to a machine's I/O bus in a bus-master role. This allows the file system and I/O devices of a failed machine to be accessed by another machine.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Bus-Master Service Adapter for High-Availability Computers

      Disclosed is a bus-master service adapter that provides access
to the I/O subsystem of a failed machine by another machine which is
simultaneously the source of redundancy used to attain high
availability.  This is an advanced version of a previously proposed
service adapter.  In addition to the capabilities of the service
adapter - e.g., power control and monitoring facilities - the
advanced service adapter provides access to a machine's I/O bus in a
bus-master role.  This allows the file system and I/O devices of a
failed machine to be accessed by another machine.

      The advantage of this arrangement is that as long as the I/O
subsystem of a failed machine remains operational, another running
machine can access the file system and I/O devices of the failed
machine with minimal additional software development and produce a
normal and regular  environment that a user is familiar with.  Thus,
availability and serviceability of a machine is significantly
improved.

      A bus master is a bus participant that can autonomously
communicate with other bus participants without the help of the
central processor or  any other part of the system.  This quality is
required for the scheme disclosed to work; but some bus
implementations require a functioning central CPU for any bus card to
work, including a bus master.  The system disclosed will still
operate under those conditions, but with less fault coverage because
its operation requires...